• • Wide competent in
• o hardware description language VHDL, used for digital circuitries description.
• o digital circuitries synthesis (Design Compiler, Physical Compiler – Synopsys, CTGEN – Cadence), placement and routing (Silicon Ensemble – Cadence) tools.
• • Competent in circuitries analysis and simulation tools (NANOSIM – Synopsys, SPICE, ELDO – Mentor, NCSIM, SIGNALSCAN – Cadence).
• • Knowledge of
• o C, C++, Assembler and VISUAL BASIC programming languages.
• o SystemC systems description language
• o TLM digital systems modeling
• o FPGA methodology.
• o LABVIEW/CVI environment to drive by PC the electronics measure instruments.
• o MATLAB software for data and signals management.
• o MEDICI software for electronic devices physical characterization.
• o OFFICE: Word, Excel e PowerPoint.
• o WINDOWS and LINUX

Ingegnere Elettronico

 STMicroelectronics company
• Engaged on August 2001 during thesis develop, to Not Volatile NOR FLASH Memory (GM Carla Golla) SLC division (single level bit cell).
o From January to June 2002 he works in Milan site of STM to acquire the methodology to develop NOR FLASH memory. During this period he works with 64Mbit NOR FLASH SLC memory develop team. He is in charge for the following activities :
Develop and synthesis of Microcontroller of NOR memory.
Develop of read algorithm to read out the data stored within cell memory for user operation and for device engineering.
• From September 2002 to February 2007 he works to develop NAND FLASH memory SLC device working with Asian people due partnership with Korean company. He is in charge for the following activities :
o 512Mbit device 120nm technology (6 months to South of Korea due to partnership) :
Develop of read, program and erase algorithm to manage the device for user operation and for device engineering.
Develop and synthesis of logic circuitry to manage stacked device for user operation and for device engineering.
Device debug through simulation tools.
Support to engineering of device.
o 256Mbit/128Mbit device 120nm technology STM design responsible due to partnership:
Jobs scheduling and database management.
Develop of read, program and erase algorithm to manage the device for user operation and for device engineering.
Develop of logic circuitry to manage stacked device for user operation and for device engineering.
Develop of logic circuitry to allow device engineering.
Synthesis of whole logic circuitry.
Device debug through simulation tools.
Database hardware correction during device debug.
Support to engineering, qualification and production of device.
Technical meeting at customer (INTEL, PANASONIC).
o PATENT : NAND MEMORY PROGRAM VERIFY METHODOLOGY WITH PAGE DATA COMPRESSION. It allows to improve data management reducing engineering time for production flow. All NAND devices have this feature.
o 1Gbit 90nm technology :
Device debug through simulation tools.
o 4Gbit device 70nm technology STM design responsible due to partnership :
Jobs scheduling and database management.
Develop of read, program and erase algorithm to manage the device for user operation and for device engineering.
Update of Microcontroller of NAND memory.
Develop of circuitry to store the algorithm to manage the memory for user operation and for device engineering.
Device debug through simulation tools.
Database hardware correction during device debug.
Support to engineering, qualification and production of device.
o 4Gbit device 60nm technology :
Synthesis of whole logic circuitry.
Device debug through simulation tools.
Engineering and debug on silicon using measuring instruments laboratory.
o 1Gbit device 48nm technology (device configurable by software as 512Mbit, 256Mbit or 128Mbit device):
Develop of pipeline architecture for data input and data output throughput improving.
Synthesis of whole logic circuitry.
Develop of redundancy circuitry (used to correct fail memory cells during engineering flow).
Management of develop of standard cells and custom cells library used during logic block synthesis flow.
• From March to October 2007 he works to develop NAND FLASH memory MLC device (multi level bit cell) working with Asian people due partnership with Korean company. He is in charge for the following activities :
o 24Gbit device 48nm technology :
Digital circuitries feasibility activity on going due to design approach, based on digital broadcast.
o PATENT : METHODOLOGY TO USE AGAIN LOGIC CIRCUITRIES WITHIN CONVOLUTIONAL CODE DECODER IN ORDER TO FIND THE START STATE OF TRACEBACK FLOW.
• From November 2007 he is the responsible of digital blocks to develop 8Gbit NAND FLASH memory MLC device (multi level bit cell) 48nm technology . He is in charge for synthesis of whole logic circuitry activity too. Engineering and debug on silicon using measuring instruments laboratory (2 months to South of Korea due to partnership).

 Numonyx company
• In January 2008 the memory business unit of STM becomes NUMONYX. Working for NUMONYX company, from May 2008 he is the responsible of digital blocks to develop 4Gbit NAND FLASH memory MLC device (multi level bit cell) 48nm technology . He is in charge for synthesis of whole logic circuitry activity too. Engineering and debug on silicon using measuring instruments laboratory.

• From April to September 2009 he is involved in multichip development made by 16Gbit NAND FLASH memory TLC device (3 level bit cell) 41 nm technology and external Controller. He is in charge for activities of design, debug, engineering and characterization concerning the interaction between Nand memory and Controller.

• From September 2009 he is involved to develop ONE NAND memory device 41nm / 32 nm technology (ONE NAND memory is a NAND FLASH memory with integrated RAM device, with non standard NAND functionality only.)

 Micron company
• In 2010 Numonyx is absorbed by Micron. From March 2010 he joins to Phase Change Memory (PCM) device development group to debug Imola, 1Gbit 45nm device, through vhdl fullchip simulations.
• From September 2011 he is involved to develop Kira, 8Gbit Phase Change Memory (PCM) device 22nm technology, through digital circuitries design. The activity includes design and synthesis of Read/Write decoding and Redundancy.
• From June 2012 he is involved to develop Eureka, 8Gbit Phase Change Memory (PCM) ONFI compliant device 22nm technology, through digital circuitries design. The activity includes design and synthesis of Read/Write decoding and Redundancy.
• From December 2012 he changes his work from hardware (Design Engineer group) to software (System Architecture Engineer group) develop, joining Managed Memory organization to develop innovative system architectures using programming languages C/C++, the language description of the SystemC and TLM modeling of digital systems :
o The activity includes both the eMMC’s software behavior model development that the development of new and optimized architectural software solutions for Managed Memory (MMC, UFS, Virtual Prototype, ”¦).
o From April 2014 he is involved to develop MOBS (Mobile Object Based Solution) architecture. Job include the cost-benefit analysis in order to suggest this innovative object architecture to improve performance energy and reliability of future mobile platforms.
o From August 2014 he joins to American team to develop the Abstract Memory device Aragorn. He acquired knowledge and independence of the new environment and tools non-stop discussing with American team. Using C++, SystemC and TLM he proposed, developed and debugged an improved architecture.
• From 1 March 2016, thanks to an internal Job Posting, he changes working team joining to the Nand validation SW team, assuming the role of Managed NAND Test Tools Application Developer. The activity regards the development of the SW test to validate the eMMC, using C++.

PATENT
• January 2004 : NAND MEMORY PROGRAM VERIFY METHODOLOGY WITH PAGE DATA COMPRESSION. It allows to improve data management reducing engineering time for production flow. All STMicroelectronics NAND devices have this feature.
• November 2007 : METHODOLOGY TO USE AGAIN LOGIC CIRCUITRIES WITHIN CONVOLUTIONAL CODE DECODER IN ORDER TO FIND THE START STATE OF TRACEBACK FLOW.
ADDITIONAL EXPERIENCE
• He has developed and marketed a specific and dedicated software for the technical and administrative management of assisted commercial activity.

ACTUAL POSITION
• Micron System Architecture Engineer
• Position : CCNL Employee
• Level : 7