Education 2016- STMicroelectronics, Digital designer for Automotive and Discrete Group (ADG) division. Digital IP developer and SoC assembler for MCUs targeting automotive market.

2014- 2016 Politecnico di Torino, Italy, Ph.D. student in Electronic and Telecommunication Engineering

2012-2014 Politecnico di Torino, Italy, Master Degree in Electronic Engineering Thesis: VLSI implementation of a parallel Turbo Decoder Architecture for the LTE Standard Grade: 110/110 with honors

2009-2012 Politecnico di Torino, Italy, Bachelor Degree in Electronic and Telecommunication Engineering Grade: 110/110 with honors 2009 Secondary School Diploma in scientific studies Grade: 100/100

Knowledge Analog and digital electronics; Microelectronic devices (above all MCUs); SoC design flow; Model based software design; Signal processing; Video coding

Skills Languages Italian (native language), English (B2)

Tools Adobe FrameMaker, Microsoft Visio, Latex, Office, Matlab and Simulink, Incisive-Cadence, Encounter RTL Compiler-Cadence, Spyglass- 1 Synopsys, Tessent-Mentor Graphics, ENOVIA Synchronicity DesignSync, ENOVIA Synchronicity ProjectSync Programming languages VHDL, Verilog, SystemVerilog, C and C++ language, bash scripting, Tcl language Modelling languages UML International standards ISO 26262, IP-XACT Operating Systems Linux, Windows, Mac OSX Driving licence Italian B category

Pubblications Optimizing the transform complexity-quality tradeoff for hardware-accelerated HEVC video coding. In IEEE Conference on Design and Architectures for Signal and Image Processing (DASIP), 2015 (pp. 1-6). Comparison between HEVC and Thor based on objective and subjective assessments. In International Conference on Systems, Signals and Image Processing, 23-25 may 2016, (pp. 1-4).