2013 – present Occupation or position held Consultant Main activities and responsibilities Verification of Digital and Mixed-Signal circuits for Optical Communications implemented in Asic/FPGA. Responsibilities included:  RTL verifications of DSP blocks within the top-level design using proprietary tools and SystemVerilog.  Functional verification of analog verilog models for top level mixed-signal simulations (e.g.: ADCs, DACs, Serdes, PLLs, Adaptive Voltage Suppliers and Temperature Sensors) and their programming through AMBA-APB and SPI interfaces  Bash/TCL scripting for RTL simulations and FPGA synthesis Name and address of employer Nokia (formerly Alcatel-Lucent) – Vimercate (MB), Italy Type of business or sector Optical Communications

2013 Occupation or position held Consultant Main activities and responsibilities CMOS Layout Design of circuits for Silicon Photonics applications. Responsibilities included:  Design and check (DRC and LVS) of Analog CMOS circuits like current steering DACs, Bias Circuitry, Trans-impedance Amplifiers (TIA) and Digital 'full-custom' circuits Name and address of employer ST Microelectronics – Castelletto di Cornaredo (MI), Italy Type of business or sector Telecommunications and Computing

2011-2012 Occupation or position held Consultant Main activities and responsibilities Fault Injection techniques for ICs to test their robustness against permanent (stuck-type) and transient faults. Responsibilities included:  Faults-list creation for given sub-modules within large ICs (e.g., CPU, memories and peripherals)  RTL and GL fault simulations  Fault-list extraction flow automation Name and address of employer Yogitech SPA – Via Lenin 132/p 56017 San Martino Ulmiano, Pisa (Italia) Type of business or sector Semiconductor Functional Safety

2011 Occupation or position held Consultant Main activities and responsibilities Digital design, simulation and test of FPGA and CPLD within Radio Transceiver boards for wireless communications. Responsibilities included:  VHDL design (e.g., Modems, Serial Intefaces, I2C buses, DeltaSigma modulators, Clock Management Units and glitch filters)  Document writing Name and address of employer Skytechnology s.r.l. – Via Gonin 55, 20147 Milan, Italy Type of business or sector Telecom

2010 Occupation or position held Digital FPGA Designer Main activities and responsibilities Simulation and verifications of Echo Cancellers for Digital TV (DVB-T) and FPGA design for automotive applications. Responsibilities included:  VHDL design (e.g., digital FIR, IIR, data-path and control units)  High level modelling using Matlab/Simulink  Document writing Name and address of employer Skytechnology s.r.l. – Via Gonin 55, 20147 Milan, Italy Type of business or sector Automotive, Avionics, Telecom&Photonics, Transportation, Aerospace and Health Care

2007 – 2009 Occupation or position held Mixed-Signal Designer Main activities and responsibilities Mixed-signal simulation and verifications of Base Band Interface (BBI) within cellular phones for 2G/3G standards. Responsibilities included:  Block level VHDL implementation, matlab modelling and functional verification of analog blocks within BBI (e.g., Sigma-Delta ADCs, DACs, PLL and Voltage References)  Block level VHDL implementation, matlab modelling and functional verification of digital circuit within BBI (e.g., Decimation FIR, 2G/3G Modulators, data-path and control units)  Top level Mixed-Signal RTL and GL simulations  Functional verification of whole RX and TX paths by using mixed mode VHDL/matlab simulations  BBI Test Concept implementation  Document writing Name and address of employer ST-Ericsson (formerly NXP Cellular BU), Binzstrasse 38, CH-8045 Zurich, Switzerland Type of business or sector Cellular Business Line

2007 Occupation or position held CMOS Analog Designer Main activities and responsibilities Analog RF design of a GPS/Galileo receiver. Responsibilities included:  Transistor level CMOS design of some analog circuits (e.g., IF Amplifier for all GPS/Galileo Sub- bands, hi-speed CML buffers, frequency clock divider)  Layout design  Document writing Name and address of employer TorinoWireless, Via Cardinal Massaia 83, 10147 Torino (Italy) Type of business or sector RF Mixed-Signal R&D

2005 – 2007 Occupation or position held CMOS Analog Designer Main activities and responsibilities Design of front-end electronic interfaces for nuclear physics experiments. Responsibilities included:  Transistor level full-custom design of CMOS analog circuits for measuring electric charges delivered by particle detectors (e.g., Charge Sensitive Amplifiers, Comparators with Hysteresis, Digital to Analog Converters, Deglitching-Circuitry)  Power and noise optimizations  Matlab modeling of cross-talk among adjacent particle detectors and its impact on CMOS design  Layout design Name and address of employer Istituto Nazionale di Fisica Nucleare (I.N.F.N.), Via Pietro Giuria 8, 10125 Torino (Italy) Type of business or sector VLSI Design for Nuclear Physics experiments

Education and training

2005 Title of qualification awarded PhD Principal subjects/Occupational skills covered Energy efficient VLSI Design. Name and type of organization providing education and training Politecnico di Torino, Torino, Italy

2001 Title of qualification awarded Degree in Electronic Engineering Principal subjects/Occupational skills covered Microelectronics, Optoelectronic, Mathematics. Name and type of organization providing education and training Politecnico di Torino, Torino, Italy

1993 Title of qualification awarded High School Diploma in Electronics Name and type of organization providing education and training I.T.I.S. E. Majorana, Grugliasco (Torino), Italy

Personal skills and competences Languages Italian Mother tongue English Good. German Basic

Technical skills and competences Analog and Digital CMOS Design, Energy Efficient VLSI Design, FPGA programming, Mixed-Signal Verification. Other skills and competences VLSI Design for Testability, Optelectronics, Nonlinear System theory and Modelling, RISC Microprocessor architectures (OpenRisc, OpenSparc T1, LEON), SoC Protocols (AMBA-AHB/APB, SPI, PCI and PCIe), DSP for Wireless Communications and Digital TV (DVB-T standard) ASIC/FPGA Design and Verification Tools Hardware Description languages: −VHDL −Verilog −SystemVerilog/UVM: SVA, Object Oriented-TB, Constrained Random Stilumus Generation, Coverage, RTL design −Spice −Common Power Format (Cadence) Professional C.A.D. tools: −Synopsys: DC/PT-Shell, Primetime, Design Analyzer, Module-Compiler −Cadence: Analog Artist, Virtuoso Layout, Layout XL, Silicon Ensemble, Assura DRC/LVS/RCX, Verifault XL, Cadence Incisive tools suite (ncvlog, ncvhdl, ncelab, ncsim, simvision), Encounter RTL Compiler/Constraint Designer/Conformal Low Power − Mentor Graphics: Modelsim/Questasim, HDL Designer − Matlab&Simulink: FdaTool, HDL Coder, DSP tools −Altera: Quartus II −Lattice: Diamond, Synplify-Pro (Lattice version) −Xilinx: Vivado Computer and Software skills −Programming languages: C, Java, Assembler 8085/8086 −Scripting languages: Matlab, Perl, Php, TCL/TK, HTML, C-shell, Bash script − Office: MS Office(Word, Power Point, Excel), OpenOffice − O.S.: MS Windows XP/7/8, SunOs 8 (CDE enviroment), Linux