TECHNICAL SKILLS
Proficient in: programming and OOP (C, C++ and Python), RTL (SystemVerilog and VHDL), statistical data processing and modelling (Matlab), scripting (bash, Tcl, Python)

EDUCATION

PhD, Computer Engineering Jan 2010 – Dec 2012
Politecnico di Milano, Milano, Italy Grade: With honors

I received the EECS PhD for my research work on modeling and mitigating time-dependent variability of advanced semiconductor nodes, with a dissertation entitled ”Exploring thermal and reliability aspects in high performance processors” (abstract follows).
Technology scaling, manufacturing advances and enhanced design methodologies have driven the increasing integration capability of CMOS devices. Sustainable performance increases, and nowadays chips can host billion transistors and more. Nevertheless, power consumption cannot be overseen, and has to be compromised with performance for optimal operation. As a matter of fact, increasing power density makes devices hotter and less reliable: it is known that 50% of failures in IC designs is due to thermal issues. Thus, thermal/reliability metrics are now set aside to the classical power/performance trade-off. VLSI integration thus relies on the reliability of the circuits itself, and with technology scaling several failure mechanisms are mining the dependability of the system, Negative Bias Temperature Instability (NBTI) representing one of the most serious concern. Mutual influence of these parameters and process variation leads to two types of
variability: ”time-0” variability and ”dynamic” variability. The former refers to the heterogeneity of electrical characteristics among subsets of the devices, and depends basically on manufacturing technology. 
The latter class, on the other hand, is driven by dynamically changing operating conditions (e.g., temperature and power). These are due to performance and power profiles that adapt to the incoming data and processes.
Design-time optimization covers a limited subset of the operating conditions, because of the estimation cost and the inability to predict any application scenario; waiting for the real hardware to be available increases the cost of the design and decreases the probability of optimization success. On the other hand, run-time
techniques are useful for dynamic adaptation to changing conditions, but their evaluation is laborious. For these reasons, design-time and run-time choices should provide a joint optimization framework, where tools, methodologies and techniques can be evaluated, estimated and optimized. The design-time domain in this context will then provide estimation capabilities of power, performance, thermal and reliability aspects, such that the output from run-time strategies (again, evaluated using design-time methodologies) lead to a closed-loop rethinking of the strategies, to cover a broader optimization space. The presented research work is driven by this, and solutions are proposed in this direction. Several features that are of utmost importance in the current technology node are addressed: multi-core processors; reliability and aging; estimation and simulation flows.

MSc, Computer Engineering Sep 2006 – Apr 2009
Politecnico di Milano, Milano, Italy Grade: 110/110 cum Laude
I designed an NoC-based embedded system that could reliably connect independent bus-based subsystems, running with Microblaze processors. The design has been implemented on Spartan 3, Virtex-II Pro, Virtex-4 and Virtex-5 faimilies supporting external dynamic partial reconfiguration.

MSc, Computer Engineering Mar 2007 – May 2008
University of Illinois at Chicago, Chicago, USA GPA: 3.9/4.0
I designed and implemented a reliable Network-on-Chip for dynamically reconfigurable systems, adopting the partial dynamic reconfiguration methodology (EAPR flow). The NoC architecture could adapt at run-time by means of topology reconfiguration.

BSc, Computer Engineering Sep 2003 – Sep 2006
Politecnico di Milano, Milano, Italy Grade: 93/110
I joined the DRESD (Dynamic Reconfigurability for Embedded Systems Design) research group within the ECE department, and gained hands-on experience with Xilinx FPGA implementation and debug. I designed and prototyped a Software-controlled dynamic relocation filter for IP Cores deployed on Spartan-3 devices.

PROFESSIONAL EXPERIENCE

FPGA Design Engineer Jul 2017 – present
Micron Semiconductor Italia srl, Vimercate, Italy
As part of the Mobile Business Unit team, I work on RTL design and functional verification of FPGA-based memory controllers, to test emerging memory systems. In addition, I contribute to the on-board functional validation and Software development.

Research Scientist Jul 2014 – Dec 2016
imec vzw, Leuven, Belgium
Scientific and technical responsible for the EU funded FP7 HARPA project. Conducting research on analysis, modelling and mitigation of BTI-induced degradation in digital circuits. Strong emphasys is given on the system-level perspective. I also work on modelling system-level reliability of complex platforms, measuring through an ad-hoc setup the fault rate of ARM commercial processors.

Digital Design Engineer Jan 2013 – Jun 2014
Yogitech spa, Vimercate, Italy
Maintenance of safety-critical digital IPs based on ARM Cortex-M and Cortex-R processors. Involved in
different activities: bug fixing, functional verification and fault-injection campaigns. Design, development
and verification of Firmware BIST for ARM Cortex-M and Cortex-R processors.

Visiting Research Scientist Aug 2012 – Dec 2012
Chalmers Tekniska H¨ogskola, G¨oteborg, Sweden
Exploring design challenges and opportunities of DRAM memory controllers for many-core architectures.

Research Scientist (PhD Candidate) Jan 2010 – Dec 2012
Politecnico di Milano, Milano, Italy
Analysis, modelling and mitigation of time-dependent variability of scaled CMOS technology in highperformance processors.

R&D Engineer Apr 2009 – Dec 2009
CEFRIEL, Milano, Italy
Analysis and optimization of power consumption and QoS of nodes within a Wireless Sensors Network.

TRAINING
• Micron training on ”A simple introduction to Error Correcting Codes: BCH and LDPC”, April 2018
• Xilinx training on ”Verification with SystemVerilog”, July 2019

PERSONAL INTERESTS
Hiking and mountaineering, digital landscape and night photography, guitar playing, music, travelling, running, languages.